View HDD32M72B9_648951.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HANBit
HDD32M72B9
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM Part No. HDD32M72B9
GENERAL DESCRIPTION
The HDD32M72B9 is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD32M72B9 is a SO-DIMM(Small Outline Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance m emory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification HDD32M72B9 - 16B HDD32M72B9 - 13A HDD32M72B9 - 13B : : : 166MHz (CL=2.5) 133MHz (CL=2) 133MHz (CL=2.5)
* 256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM with ECC * 2.5V 0.2V VDD and VDDQ power supply * Auto & self refresh capability (8192 Cycles/64ms) * All input and output are compatible with SSTL_2 interface * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Burst type : Sequential & Interleave * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * The used device is 8M x 8bit x 4Banks DDR SDRAM * Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh) * Serial Presence detect with EEPROM
URL : www.hbe.co.kr REV 1.0 (July. 2003)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 PIN 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 Frontl DQ27 VDD CB0 CB1 Vss DQS8 CB2 VDD CB3 NC VSS CK2 /CK2 VDD CKE1 NC(A13) A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD PIN 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 Back DQ31 VDD CB4 CB5 Vss DM8 CB6 VDD CB7 NC(/RESET) VSS VSS VDD VDD CKE0 NC (BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS NC NC VSS DQ36 DQ37 VDD PIN 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 *These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN A0~A12 BA0~BA1 DQ0~DQ63(CB0~CB7) DQS0~DQS8 DM0~DM8 CK0~CK2,/CK0~/CK2 CKE0~CKE1 /CS0 /RAS, /CAS NC
URL : www.hbe.co.kr REV 1.0 (July. 2003)
HDD32M72B9
Front DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID
PIN 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Back DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD *SA0 *SA1 *SA2 NC
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(2.3V~3.3V) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD identification flag
HANBit Electronics Co.,Ltd.
Address input Bank Select Address Data input/output (Check Bit Data In/Out) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row / Column Address strobe No connection
2
VDD VDDQ VREF VDDSPD VSS SA0~SA2 SDA SCL WP VDDID
HANBit
FUNCTIONAL BLOCK DIAGRAM
HDD32M72B9
URL : www.hbe.co.kr REV 1.0 (July. 2003)
3
HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD32M72B9
Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external
/CS
Chip Select
bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe Column strobe Write enable address
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge.
/CAS
/WE
Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0 ~ 8
Data Strobe
tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~8
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63 CB0 ~ 7 VDDQ VDD VSS
Data input/output Check Bit Supply Supply Supply
Data inputs/outputs are multiplexed on the same pins. Check Bits for ECC data are multiplexed on the same pins. DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground.
VREF VDDSPD VDDID
Supply Supply
SSTL_2 reference voltage. Serial EEPROM Power Supply : 3.3v VDD identification Flag
URL : www.hbe.co.kr REV 1.0 (July. 2003)
4
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Voltage on V DDQ supply relative to Vss Storage temperature Power dissipation Short circuit current SYMBOL VIN, VOUT VDD VDDQ TSTG PD IOS RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 8.0 50
HDD32M72B9
UNTE V V V C W mA
Notes : Permanent device damage may occur if ABSOLUTE MAXIUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 IN/OUT)
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) )
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (Normal Strenth driver (VOUT = VTT + 0.84V) Output Low current (Normal Strenth driver (VOUT = VTT - 0.84V) Output High current (Normal Strenth driver (VOUT = VTT + 0.45V) Output Low current (Normal Strenth driver (VOUT = VTT - 0.45V) Notes : 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF,bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. A 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. I OL 9 mA I OH -9 I OL 16.8 SYMBO L VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH MIN 2.3 2.3 VDDQ/2-50mV VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8 MAX 2.7 2.7 VDDQ/2+50mV VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 UNIT V V V V V V V V uA uA mA 3 5 1 2 4 4 NOTE
URL : www.hbe.co.kr REV 1.0 (July. 2003)
5
HANBit Electronics Co.,Ltd.
HANBit
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25C)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 Normal IDD6 Low power IDD7A 14 2,920 14 2,520 14 2,520 16B(DDR333@CL=2.5) 810 1080 27 225 80 315 495 1,530 1,530 1,620 27 13A(DDR266@CL=2) 720 990 27 180 165 270 405 1,260 1,260 1,480 27
HDD32M72B9
13B(DDR266@CL=2.5) 720 990 27 180 165 270 405 1,260 1,260 1,480 27
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
Optional
Module IDD was calculated on the basis of component I DD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs STMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2
MIN
VREF + 0.31
MAX
UNIT
NOTE
3
VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2
V V V
3 1 2
Notes:
1. 2. 3.
VID is the magnitude of the difference between the input level on CK and the input on CK*. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition
URL : www.hbe.co.kr REV 1.0 (July. 2003) 6
VALUE 0.5 * VDDQ 1.5 VREF+0.31/VREF-0.31 VREF+0.35/VREF VREF VTT See Load Circuit
UNIT V V V V V V V
NOTE
HANBit Electronics Co.,Ltd.
HANBit
HDD32M72B9
CAPACITANCE
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25C, f = 100MHz)
DESCRIPTION SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 MIN MAX 44 44 42 38 9 9 9 UNITS pF pF pF pF pF pF pF
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE) Input capacitance(CKE0,CKE1) Input capacitance(/CS0) Input capacitance(CK0~CK2, /CK0~/CK2) Input capacitance(DM0~DM8) Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7) Input capacitance(CB0~CB8)
URL : www.hbe.co.kr REV 1.0 (July. 2003)
7
HANBit Electronics Co.,Ltd.
HANBit
AC CHARACTERISTICS (These AC charicteristics were tested on the Component)
DDR333 PARAMETER SYMBOL -16A MIN Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK* Output data access time from CK/CK* Data strobe edge to ouput data edge Read Preamble Read Postamble tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tCK 6 0.45 0.45 -0.6 -0.7 0.9 0.4 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 7.5 0.45 0.45 tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD 60 72 42 18 18 12 15 1 1 7.5 12 70K MAX DDR266A -13A MIN 65 75 45 20 20 15 15 1 1 7.5 12 120K MAX
HDD32M72B9
DDR266B -13B MIN 65 75 45 20 20 15 5 1 1 10 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 120K MAX ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK 5 5 5 UNIT NOTE
-0.75 -0.75 0.9 0.4
CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input hold time(slow) Address and Control Input hold time(slow) Data-out high impedance time from CK/CK* Data-out low impedance time from CK/CK* Input Slew Rate(for input only pins)
URL : www.hbe.co.kr REV 1.0 (July. 2003)
tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I)
0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 075 0.8 0.8 -0.7 -0.7 0.5
8
1.25
0.75 0 0.25 0.2 0.2 0.35 0.35
1.25
0.75 0 0.25 0.2 0.2 0.35 0.35
1.25
tCK ns tCK tCK tCK tCK tCK 2
1.1
0.9 0.9 0.9 10 1.0
1.1
0.9 0.9 0.9 1.0 1.0
1.1
tCK ns ns ns ns 6 6 6 6
+0.7 +0.7
-0.75 -0.75 0.5
+0.75 +0.75
-0.75 -0.75 0.5
+0.75 +0.75
ns ns V/ns 6
HANBit Electronics Co.,Ltd.
HANBit
Input Slew Rate(for I/O pins) Output Slew Rate (x4, x8) Output Slew Rate Matching Ratio(rise to fall) Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Control & Address input pulse width Exit self refresh to bank active command Exit self refresh to non-read command Exit self refresh to read command Refresh interval time Output DQS valid window tSL(IO) tSL(O) tSLMR tMRD tDS tDH tDIPW tPDEX tIPW tXSA tXSNR tXSRD TREFI TQH 0.5 1.0 0.67 12 0.45 0.45 1.75 6 2.2 80 75 200 7.8 tHPmi n -tQHS tCLmi n or tCHS 0.55 0.4 20 0.6 0.4 20 (tWR/t CK) + (tRP/t CK) Notes : 1. 2. Maximum burst refresh cycle : 8 4.5 1.5 0.5 1.0 0.67 15 0.5 0.5 1.75 7.5 2.2 75 75 200 7.8 tHPmi n -tQHS tCLmi n or tCHS 0.75 0.6 0.4 20 4.5 1.5 0.5 1.0 0.67 15 0.5 0.5 1.75 7.5 2.2 75 75 200
HDD32M72B9
V/ns 4.5 1.5 ns ns ns ns ns ns ns ns tCK us ns 1 5 4 7,8,9 7,8,9 V/ns 7 10
Clock half period THP Data hold skew factor DQS write postamble time Active to Read with Auto precharge TRAP command Autoprecharge write recovery + Precharge time TDAL TQHS TWPST
7.8 tHPmi n -tQHS tCLmi n or tCHS 0.75 0.6
ns ns tCK 3
(tWR/t CK) + (tRP/t CK)
(tWR/t CK) + (tRP/t CK) 1CK 11
The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previou s write was in progress, DQS could be High at this time, depending on tDQSS.
3. 4. 5. 6.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade acc ordingly. A write command can be applied with tRCD satisfied after this command. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter ( tJIT(HP)) of the PLL A and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 .tIS (ps) 0 +50 +100
9
.tIH (ps) 0 +50 +100
HANBit Electronics Co.,Ltd.
URL : www.hbe.co.kr REV 1.0 (July. 2003)
HANBit
setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating. Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 .tDS (ps) 0 +75 +150 .tDH (ps) 0 +75 +150
HDD32M72B9
This derating table is used to increase t IS /t IH in the case where the input slew rate is below 0.5V/ns. I nput
This derating table is used to increase t DS /t DH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating. I/O Input Level (mV) 280 duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating. Delta Rise/Fall Rate (V/ns) 0 0.25 0.5 .tDS (ps) 0 +50 +100 .tDH (ps) 0 +50 +100 .tDS (ps) +50 .tDH (ps) +50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC -AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design.
URL : www.hbe.co.kr REV 1.0 (July. 2003)
10
HANBit Electronics Co.,Ltd.
HANBit
SIMPLIFIED COMMAND TRUTH TABLE
COMMAND Register Register Extended MRS Mode register set Auto refresh Refresh Self refresh Entry Exit CK E n-1 H H H L H precharge H precharge precharge H X L H L L H Bank selection All banks Entry Exit Entry Exit H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X V X L H X X L H L H X V CK E n X X H L H X /CS L L L L H L /R A S L L L H X L /C A S L L L H X H
HDD32M72B9
(V=VALID, X=DON C T CARE, H=LOGIC HIGH, L=LOGIC LOW)
/WE L L H H X H
DM X X X X X
BA 0,1
A10/ AP OP code OP code X X
A11 A9~A0
NOTE 1,2 1,2 3 3 3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharg e Auto disable Auto precharge eable Auto disable Auto enable
V
Row address L H Column Address (A0 ~A9) Column Address H X X (A0 ~ A9) 4,6 7 5 4 4 4
H X V
L
Clock suspend or active power down
Precharge power down mode DM
8 9 9
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.. 6. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0) 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
11 HANBit Electronics Co.,Ltd.
URL : www.hbe.co.kr REV 1.0 (July. 2003)
HANBit
PACKAGING INFORMATION
Unit : mm
HDD32M72B9
Front - Side
Z
Y
PCB
: 1.0 0.1mm
ORDERING INFORMATION
Part Number
Density
Org.
Package 200PIN SO-DIMM 200PIN SO-DIMM 200PIN SO-DIMM
Ref.
Vcc
MODE
MAX.frq
HDD32M72B9-16B HDD32M72B9-13A HDD32M72B9-13B
256MByte 256MByte 256MByte
32M x 72 32M x 72 32M x 72
8K 8K 8K
2.5V 2.5V 2.5V
DDR DDR DDR
166MHz/CL2.5 133MHz/CL2 133MHz/CL2.5
URL : www.hbe.co.kr REV 1.0 (July. 2003)
12
HANBit Electronics Co.,Ltd.

▲Up To Search▲

Price & Availability of HDD32M72B9

	To Download HDD32M72B9 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .